?MS or PhD in Electrical Engineering 電子工程專業(yè)碩士或博士學(xué)歷 ? 5+ years of experience working with analog/mixed-signal/digital circuits. Strong background in high-speed analog and mixed signal integrated circuit design 5年以上在模擬或模數(shù)混合信號電路設(shè)計方面的相關(guān)工作經(jīng)驗(yàn)，具有高速模擬和混合信號集成電路設(shè)計的背景 ? Strong command of fundamental concepts such as circuit noise and linearity 對集成電路設(shè)計中的基本概念比如電路噪聲、線性等有很強(qiáng)的理解能力 ? Experience in Si CMOS and SiGe BiCMOS technologies to design high-speed circuits: linear amplifiers, low noise linear TIAs, AGC circuits, linear equalizers 有Si CMOS和SiGe BiCMOS技術(shù)的經(jīng)驗(yàn)去設(shè)計高速電路包括：線性放大器、低噪聲線性跨阻放大器、AGC電路，線性均衡器 ? Experience in testing and debugging analog and mixed signal high-speed ICs 具有模擬和混合信號高速集成電路的測試和調(diào)試經(jīng)驗(yàn) ? familiarity with SerDes, CDR, PLL, ADC, DAC, bandgap, LDO blocks 熟悉SerDes, CDR, PLL, ADC, DAC, bandgap, LDO blocks ? Familiarity with digital flow (synthesis, static timing, place and route), particularly in the context of state machines for mixed-signal control systems 熟悉數(shù)字設(shè)計流程（合成、靜態(tài)時序、布局及路線固定），特別是對于在混合信號的控制系統(tǒng)中的控制狀態(tài)機(jī) ? Familiarity withserial/parallel communication protocols (e.g., SPI, I2C). 熟悉串行/并行通信協(xié)議（例如SPI、I2C） ?Experience with physical design and verification, passive component design using industry-standard tools such as Cadence Virtuoso and EMX. 有實(shí)體設(shè)計和驗(yàn)證的經(jīng)驗(yàn)，能夠使用工業(yè)標(biāo)準(zhǔn)工具設(shè)計無源元件例如Cadence和EMX
投遞簡歷
400
